Power management during wakeup
US9270262B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jan 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first set of transistors and a second set of transistors. The first set of transistors is configured to be turned on in a sequential manner. The second set of transistors is configured to be turned on in a sequential manner after the first set of transistors is turned on. A transistor of the first set of transistors corresponds to a first time delay. The first set of transistors corresponds to a second time delay that is a multiple of the first time delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.