Clock gating circuit for reducing dynamic power
US9270270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate. The control circuit has inputs to receive an input clock signal, a clock enable signal, and a clock gating control signal, and has an output terminal to generate a latch enable signal. The latch has a data terminal responsive to the clock enable signal, a latch enable terminal responsive to the latch enable signal, and an output to generate the clock gating control signal. The logic gate has inputs to receive the input clock signal and the clock gating control signal, and has an output terminal to generate an output clock signal. The clock-gating circuit may reduce power consumption during an enabled state by maintaining the latch enable signal at a constant logic state, thereby reducing dynamic power consumption by preventing internal logic gates from dynamically switching logic states while the input clock signal is gated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.