Integrated sensor array with offset reduction
US9274179B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Oct 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R33/075
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for providing increased accuracy in a CMOS sensor system in one embodiment includes a plurality of sensor elements having a first terminal and a second terminal on a complementary metal oxide semiconductor substrate, a first plurality of switches configured to selectively connect the first terminal to a power source and to selectively connect the first terminal to a readout circuit, and a second plurality of switches configured to selectively connect the second terminal to the power source and to selectively connect the second terminal to the readout circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.