Method and apparatus for error management of an integrated circuit system
US9274909B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Dec 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.