Sideband logic for monitoring PCIe headers
US9274915B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | May 19, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Aug 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.