Gate drive circuit, array substrate and display apparatus
US9275589B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 30, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3655
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate drive circuit, comprising: a plurality of shift register units each having a signal output end, wherein the signal output end of one of the plurality of shift register units except the last one is connected to the signal input end of the next one; L arithmetic units each having a plurality of input ends, wherein L is an integer equal to or larger than 2, and one of the plurality of input ends of each of the L arithmetic units is connected to the signal output end of a respective shift register unit; and a clock generation unit having a plurality of clock output ends for outputting different clock signals, wherein at least one of the plurality of clock output ends is connected to at least one of the other input ends of a respective arithmetic unit except the one input end connected to the signal output end of the shift register unit, so that the L arithmetic units output L different drive signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.