Split bit line architecture circuits and methods for memory devices
US9275721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2010 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Nov 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.