Method of manufacturing a junction electronic device having a 2-dimensional material as a channel
US9275860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | May 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a junction electronic device having a 2-Dimensional (2D) material as a channel, includes forming a pattern portion by surface-treating a substrate so that the patterned portion has a higher surface potential than other portions of the substrate; bonding a 2D material to rthe patterned portion having the higher surface potential by spraying a liquid including 2D material flakes onto the substrate; forming a pair of first electrodes in contact with both ends of the 2D material disposed on the substrate; forming a dielectric layer on the first electrodes and the 2D material; and forming a second electrode on the dielectric layer. The 2D materials are disposed at desired positions by chemical exfoliation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.