Method of manufacturing element substrate
US9276019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2012 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Dec 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1345
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an array substrate 20 according to the present invention includes a line forming step, and line forming step includes following performances. A plurality of source lines 27 are formed on a glass substrate GS so as to extend from a first region A1 on the glass substrate GS to a second region A2 that is adjacent to the first region on an outer side thereof. A plurality of source driver side check lines 45A are formed on the glass substrate GS so as to extend from the second region A2 to a third region that is adjacent to the first region A1 on an outer side thereof and adjacent to the second region A2. A plurality of first line connection portions 49 are formed in the second region A2 and the first line connection portions 49 connect the source lines 27 and the first source driver side check lines 45A. A capacity stem line 43 and a common line 44 are formed to extend from the first region A1 to the third region A3. A second source driver side check line 45B and a second line connection portion 50 that connects each of the capacity stem line 43 and the common line 44 and the source driver side check line 45B are formed in the third region A3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.