Memory elements with stacked pull-up devices
US9276083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.