Vertical memory devices and method of manufacturing the same
US9276133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Feb 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.