Duty ratio correction circuit and phase synchronization circuit
US9276565B2 · kind B2 · utility
2Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.