High-performance low-power near-Vt resistive memory-based FPGA
US9276573B2 · kind B2 · utility
2Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jul 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.