Low leakage state retention synchronizer
US9276575B2 · kind B2 · utility
1Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Mar 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit, and an output, wherein the second memory unit operates on a second power supply which is always on; and a control logic coupled to the first and second memory units, the control logic to provide one or more control signals to each of the first and second memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.