Generating signals with accurate quarter-cycle intervals using digital delay locked loop
US9276590B1 · kind B1 · utility
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3References
19Claims
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Key dates
| Filing date | Nov 11, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a delay circuit and a control circuit. The delay circuit may be configured to generate a plurality of intermediate signals in response to (i) a clock signal and (ii) an adjustment signal. The control circuit may be configured to generate the adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) the plurality of intermediate signals and (ii) the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.