Method and apparatus of a fully-pipelined layered LDPC decoder
US9276610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jan 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/116
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.