Generating a wafer inspection process using bit failures and virtual inspection
US9277186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jan 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.