Method and system for re-ordering bits in a memory system
US9280454B1 · kind B1 · utility
7Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2012 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Jul 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for re-ordering bits in a memory system is disclosed. The memory system includes a system on a chip (SoC) coupled to a plurality of memory chips. Each of the memory chips including a memory array, multipurpose registers (MPRs) coupled to the memory array; and a data bus coupled between the SoC and the memory array. The method and system comprise utilizing the MPRs within each of the plurality of memory chips to determine bit ordering within each byte lane of memory array of the associated memory chip. The method and system further includes providing the determined bit ordering to the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.