Formal verification of arbiters
US9280496B2 · kind B2 · utility
3Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2012 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Mar 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implement method, computerized apparatus and computer program product for formal verification of an arbiter design. The method comprising: performing formal verification of an arbiter design, wherein the arbiter design is based on an original arbiter design comprising a fairness logic and an arbitration logic, wherein the arbiter design comprising the arbitration logic and a portion of the fairness logic; and wherein the formal verification is performed with respect to a multi-dimensional Complete Random Sequence (CRS) having two or more dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.