Data interface sleep mode logic
US9280509B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus may include a rising edge detector to detect a rising edge in a signal. The apparatus may also include a counter to perform a count to a first value based on an input clock signal. The apparatus may also include an output unit to generate a sleep signal after the first value is reached if the rising edge detector does not detect the rising edge in the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.