Patent · US Active

Inter-chip communications with link layer interface and protocol adaptor

US9280510B2 · kind B2 · utility

4Cited by

4References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sridharan Ranganathan · San Ramon, US
David J. Harriman · Sacramento, US
Anoop Mukker · Folsom, US
Satheesh Chellappan · Folsom, US
Karthi R. Vadivelu · Folsom, US
Shalini Sharma · Bengaluru, IN
Zeeshan Sarwar · Folsom, US

Key dates

Filing date	Jan 20, 2015
Grant date	Mar 8, 2016
Priority date	—
Expiry date	Jan 20, 2035

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.