Content addressable memory
US9280633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | May 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.