Method and apparatus for read assist to compensate for weak bit
US9281031B2 · kind B2 · utility
8Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2015 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.