Patent · US Active

Memory system and an apparatus

US9281053B2 · kind B2 · utility

0Cited by

5References

16Claims

0Family size

Assignee

Huawei Technologies Co., Ltd. · CN

Inventors

Rami Zecharia · Munich, DE
Yaron Shachar · Raanana, IL

Key dates

Filing date	Mar 5, 2014
Grant date	Mar 8, 2016
Priority date	—
Expiry date	May 20, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/2532
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.