Flash memory device and flash memory system including the same
US9281072B2 · kind B2 · utility
2Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2015 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Sep 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.