Single poly non-volatile memory cells
US9281313B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2012 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Apr 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
Abstract
A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.