System and method for multi standard programmable LDPC decoder
US9281840B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Mar 14, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Jun 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for implementing multi standard programmable low-density parity check decoder in a receiver is provided. The method includes (i) generating, by a control signal generation unit, pre computed control signals associated with a h-matrix, (ii) obtaining, by a control signal storage unit of a hardware decoder unit, the pre computed control signals associated with the h-matrix, (iii) obtaining, by a LLR memory fetch & data align unit, LLR bytes from a LLR memory unit, (iv) rotating, by a rotation and aligning unit, the LLR bytes to obtain aligned valid LLR bytes, (v) processing, by the processing element unit, the aligned valid LLR bytes to obtain an output data, and (vi) decoding, the h-matrix associated with at least one standard and code rates based on the pre computed control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.