Systems and methods for DQS gating
US9285824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2013 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Feb 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a falling edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.