Data processing apparatus having a parallel processing circuit including a plurality of processing modules, and method for controlling the same
US9286078B2 · kind B2 · utility
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3References
18Claims
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Key dates
| Filing date | Apr 28, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Apr 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an apparatus which includes a plurality of processing modules connected via a ring-shape bus, if a plurality pieces of pipeline processing to be processed in a different order is allocated to a plurality of processing modules, the transfer efficiency may decrease when an amount of data transferred from one of the processing modules to a post-stage module exceeds a processing capacity of the post-stage module. Accordingly, a module positioned on the preceding side in the pipeline processing controls a transmission interval of processed data so that the post-stage module can receive the data processed by the preceding module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.