Heterogeneous memory system
US9286221B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2015 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterogeneous memory system includes a main memory arrangement, a first-level cache, a second-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and the second-level cache includes a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the first-level cache or the second-level cache for storage of the first data and stores the first data in the selected one of the first or second-level caches. The MMU reads second data from one of the first-level cache or second-level cache and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.