Constraining prefetch requests to a processor socket
US9286224B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Mar 12, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.