Method and apparatus for testing
US9286426B2 · kind B2 · utility
3Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Apr 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.