Memory refresh method and devices
US9286965B2 · kind B2 · utility
6Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2011 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Jul 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.