Mitigating read disturb in a cross-point memory
US9286975B2 · kind B2 · utility
14Cited by
0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Mar 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.