Semiconductor memory device and system having redundancy cells
US9287004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2012 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Apr 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.