SIC epitaxial wafer and method for manufacturing same
US9287121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2012 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a SiC epitaxial wafer wherein a SiC epitaxial layer is provided on a SiC single crystal substrate having an off angle. The method includes determining a ratio of basal plane dislocations (BPD) which cause stacking faults in a SiC epitaxial film of a prescribed thickness, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, determining an upper limit of surface density of basal plane dislocations, preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.