Patent · US Active

Resonant clocking for three-dimensional stacked devices

US9287196B2 · kind B2 · utility

1Cited by

0References

14Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ruchir Saraswat · Swindon, GB
Uwe Zillmann · Braunschweig, DE
Andre Schaefer · Hersbruck, DE
Tor Lund-Larsen · Braunschweig, DE

Key dates

Filing date	Dec 28, 2012
Grant date	Mar 15, 2016
Priority date	—
Expiry date	Feb 7, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.