Stacked bias I-V regulation
US9287830B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Aug 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45116
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A RF amplifier circuit including a plurality of FET devices, where a source terminal of an FET device is electrically coupled to the drain terminal of another FET device. The circuit further includes a voltage divider network and a plurality of operational amplifiers, where a separate one of the operational amplifiers is provided for each FET device. Each operational amplifier includes a positive input terminal, a negative input terminal and an output terminal, where the output terminal for a particular operational amplifier is electrically coupled to a gate terminal of a particular FET device, the negative input terminal of each operational amplifier is electrically coupled to the source terminal of the particular FET device and the positive input terminal of each operational amplifier is electrically coupled to the voltage divider network. A source resistor is electrically coupled to the source terminal of a bottom FET device in the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.