Signal conversion circuit, PLL circuit, delay adjustment circuit, and phase control circuit
US9287853B2 · kind B2 · utility
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3References
10Claims
0Family size
Assignee
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Key dates
| Filing date | May 23, 2012 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | May 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.