Low leakage shadow latch-based multi-threshold CMOS sequential circuit
US9287858B1 · kind B1 · utility
3Cited by
5References
20Claims
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Key dates
| Filing date | Oct 23, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Oct 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.