Data receiver circuit and method of adaptively controlling equalization coefficients using the same
US9288087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2012 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | May 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Provided are a data receiver circuit and a method of adaptively controlling an equalization coefficient using the same. The data receiver circuit includes n sampling receivers, n decision feedback equalizer (DFE) circuits, and a data recovery circuit. The n sampling receivers are configured to sample an input signal and output n respective sampling signals in response to n respective clock signals. The n DFE circuits are configured to equalize the n respective sampling signals in response to a DFE control signal and generate n respective pre-recovery signals in response to the n equalized sampling signals and n respective previous pre-recovery signals, the DFE control signal for changing an equalization ability of the n DFE circuits. The data recovery circuit is configured to select one of the n respective pre-recovery signals, and output the selected n pre-recovery signal as a recovered input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.