Activity-driven capacitance reduction to reduce dynamic power consumption in an integrated circuit
US9292648B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Sep 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.