Partition-free multi-socket memory system architecture
US9292900B2 · kind B2 · utility
0Cited by
15References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | May 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.