Memory test device and operating method thereof
US9293226B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Jul 28, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jul 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.