Constant GM bias circuit insensitive to supply variations
US9294039B2 · kind B2 · utility
0Cited by
2References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Mar 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias circuit for biasing a field effect transistor (FET) to provide a transconductance (gm) that is substantially unaffected by power supply voltage variations. In one embodiment the circuit includes two parallel current paths, each including two amplifying elements such as FETs, the FETs in one of the paths both being diode-connected, and the FETs in the other path not being diode-connected. Variations in the power supply voltage result in comparable changes in the voltage drops across all four FETs, and drain-induced barrier lowering (DIBL) results in relatively small changes in gm with changes in power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.