Level shift circuit utilizing resistance in semiconductor substrate
US9294093B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2015 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jan 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus such as a level shift circuit includes a first signal output device configured to output a first level shifting signal, a second signal output device configured to output a second level shifting signal, and first and second detector devices. The level shifting signals are to control an output switching element of a high potential side of an output device that includes a power source and a load. The first and second detector devices are respectively configured to compare the first and second level shifting signals to a reference signal and output respective first and second comparison result signals. The first and second comparison result signals are configured to at least partly control switching of the first and second level shifting signals based at least in part on the presence of a parasitic resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.