Phase-locked loop circuit with improved performance
US9294104B2 · kind B2 · utility
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9References
22Claims
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Key dates
| Filing date | Jul 16, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jul 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.