Correction circuits for successive-approximation-register analog-to-digital converters
US9294110B1 · kind B1 · utility
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5References
19Claims
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Key dates
| Filing date | Jan 29, 2015 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jan 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/765
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a correction circuit comprises circuit comprises a replica transistor biased at a current density to match that of a high side transistor of an output power switch at a specific load. A sample and hold circuit is coupled to the replica transistor to sample a voltage across the replica transistor. A differential amplifier provides a level shifted differential replica voltage to a tap of a resistor ladder of a successive approximation register analog-to-digital converter in response to the sampled voltage across the replica transistor. A current source provides a current to a top of the resistor ladder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.