Methods and systems for reducing order-dependent mismatch errors in time-interleaved analog-to-digital converters
US9294112B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Nov 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/124
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.