Dual-stage data decoding for non-volatile memories
US9294132B1 · kind B1 · utility
25Cited by
6References
15Claims
0Family size
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Key dates
| Filing date | Nov 8, 2012 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Oct 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/27
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for decoding information read from a non-volatile memory uses a two stage decoding algorithm, where the first stage is a high-speed, low precision decoder and the second stage is a low-speed, high precision decoder. Most of the time only the first stage of the decoder is used, which lowers the average power consumption of the decoding process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.